Design and Implementation of GDI Based Pipeline Architecture for NCO Using LUT

Authors

  • G V Ramana Reddy Department of Electronics and Communication Engineering, Varaprasad Reddy Institute of Technology, Guntur, India 522438

Keywords:

Numerically Controlled Oscillator (NCO), Coherent control, Phase Separation, Look Up Table (LUT), Gate Diffusion Input (GDI)

Abstract

Technical and economic problems are connected with the capacity extension of the grid to remote areas. Basically, Numerically Controlled Oscillator (NCO) is widely used in the applications of digital signal processing.  In this paper, the design and implementation of GDI based pipeline architecture for NCO using LUT is done. In this phase separation will separates the phase difference signal based on the input signal and the oscillated signal. NCO generates a frequency- and phase tunable output signal with a precision fixed-frequency clock. 32 bit counter will compares the current count to the value stored in the compare register. Coherent control will control the carrier synchronizer by employing data from 32 bit counter. Index compute will save the obtained data after controlling.

References

R. E. Best, Phase-Locked Loops: design, simulation, and applications, 5th ed. New York; McGraw-Hill, 2016.

Wei-Tsen Lin and Dah-Chung Chang, “The Extended Kalman Filtering Algorithm for Carrier Synchronization and the Implementation,” IEEE International Symposium on Circuits and Systems, May, 2016.

K. Gunnam et al., “New Optimizations for Carrier Synchronization in Single Carreir Systems,” IEEE International Conference on Acoustics, speech, and Signal Processing, vol. 5, pp v/661 – v/664, March 2015.

Ronald R. Stephens, Phase-Locked Loops for Wireless Communications: Digital, Analog and Optical Implementations, Second Edition, New York; Kluwer Academic Publishers, 2012.

S. Kadam, D. Sasidaran, A. Awawdeh, L. Johnson, and M. Soderstarnd, “Comparison of various numerically controlled oscillators”, The 45th Midwest Symposium on Circuits and Systems, vol. 3, pp. 200 - 202, Aug. 2012.

R. J. Andraka, “A survey of CORDIC algorithms for FPGA based computers”, Proc. ACM/SIGDA sixth international symposium on Field programmable gate arrays, pp. 191 – 200, Feb. 2011.

Liang Yi ,Yang Yuan, Yu Ningmei and Gao Yong, “The Application of a Novel Direct Digital Frequency Synthesizer for the IP Core Design of All Digital Three Phase SPWM Generator”, IPEMC, vol. 2, pp. 730-733, Aug. 2010.

Chun-Nan Ke, Cheng-Yi Huang and Chih-Peng Fan, “An Adaptive Carrier Synchronizer for M-QAM cable receiver,” IEEE International Conference on ICCE,” vol. 45, pp 290-291, June 2009.

V. Lesnikov, A. Chastikov, D. Garsh, T. Naumovich, “Numerically Controlled Linear Chirp Oscillator”, 5th Mediterranean Conference on Embedded Computing MECO 2009.

J. E. Volder, “The CORDIC Trigonometric Computing Technique”, IRE Trans. on Electronic Computers, vol. 8 no. 3, pp. 330-334, 2009.

J. Yuan, and C. Svensson, "High-speed CMOS circuit technique," IEEE J. Solid-state Circuits, Vol. 24, pp. 62- 70, Feb. 2008.

J. Yuan, C. Svensson, F. Lu, and H. Samueli, "A high-speed pipelined CMOS accumulator for implementing numerically controlled oscillators," IEEE Proc. Int'l Symp. on Circuits & Systems, pp. 113-1 16, May 2007.

J. Hauenschild, er al., "Influence of transmission-line interconnections between gigabit-per-second IC's on time jitter and instabilities," IEEE J. Solid-state Circuits, Vol. 25, pp. 763-766, June 2006.

300 MHz ECL lOOK 28-bit Resolution Numerically Controlled Oscillator, STEL-21 72 Data Sheet, Stanford Telecommunications, Inc., July 2004.

32-bit DDS Phase Accumulator, 1.0 GHz Clock Rate, lOG102 Data Sheet, GigaBit Logic, Inc., May 2003.

Additional Files

Published

2021-07-03

How to Cite

G V Ramana Reddy. (2021). Design and Implementation of GDI Based Pipeline Architecture for NCO Using LUT. International Transactions on Electrical Engineering and Computer Science, 2(2), 81-91. Retrieved from http://iteecs.com/index.php/iteecs/article/view/18

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Articles